New module: Power_Supply[ACDC-DC-1.0.0]; Fix link git in SpeedJeck-V1 PCB F.Silkscreen

2026-03-18 21:35:46 -07:00
parent 1ee649a8bd
commit 06e04d6c0a
69 changed files with 234079 additions and 4770 deletions
--- a/SpeedJeck-v1/pcb/SpeedJeck-backups/SpeedJeck-2026-03-16_201314.zip
+++ b/SpeedJeck-v1/pcb/SpeedJeck-backups/SpeedJeck-2026-03-16_201314.zip
--- a/SpeedJeck-v1/pcb/SpeedJeck.kicad_pcb
+++ b/SpeedJeck-v1/pcb/SpeedJeck.kicad_pcb
@@ -18,7 +18,7 @@
 		(comment 4 "Device charged by PC's USB.")
 		(comment 5 "5V converts into 3.3V for DATA BUS")
 		(comment 6 "Sinus")
-		(comment 7 "https://gittea.dev/SocioCybereeng/PCBs/SpeedJeck-v1")
+		(comment 7 "https://git.sociocyber.site/SocioCybereeng/PCB/src/branch/master/SpeedJeck-v1")
 	)
 	(layers
 		(0 "F.Cu" signal)
@@ -10875,8 +10875,8 @@
 		(layer "Edge.Cuts")
 		(uuid "88064688-0e0d-4b26-a83f-e5875c8dddfe")
 	)
-	(gr_text "https://gittea.dev/SocioCybereeng/PCBs/SpeedJeck-v1"
-		(at 153.8478 97.5868 0)
+	(gr_text "https://git.sociocyber.site/SocioCybereeng/PCB"
+		(at 157.8 97.4 0)
 		(layer "F.SilkS")
 		(uuid "40854733-b031-47d3-a076-74eb5e94b91b")
 		(effects
--- a/SpeedJeck-v1/pcb/fp-info-cache
+++ b/SpeedJeck-v1/pcb/fp-info-cache